1. Field of the Invention
The present invention relates to a circuit structure and a semiconductor integrated circuit having a track layout in which a plurality of terminal rows are provided and tracks are routed to interconnect terminal (signal) pairs to be connected each other and a method and a system for laying out the routing tracks.
2. Background Art
As is well known, a semiconductor integrated circuit has a variety of circuits built therein to attain desired functions, respectively, and these circuits are constituted by interconnecting a lot of circuit elements by conductor tracks. For example, when a gate array approach is adopted for production of large scale integrated circuits (hereinafter referred to as LSI), a common mask is used throughout the processing steps including a diffusion process, except the last processing step where different masks are used in separate production runs for providing specific routing tracks or wiring interconnections in the respective chips. This approach enables a variety of chips to be produced within a remarkably shortened time.
FIG. 8 shows diagramatically a master slice LSI.
As shown in FIG. 8, various circuit elements are provided on a chip 80. More specifically, bonding pads 83 are arranged along the periphery of the square chip for permitting connection to the outside. Upper and lower annex circuit areas 82 and a plurality of cell rows 1 and wiring areas 81 are provided within a space defined by encircling train of bonding pads 83. The cell rows 1 and wiring areas 81 are arranged alternately. Each cell row 1 has transistors, resistors and other circuit elements built in the form of unit cells 84.
It is necessary to determine or route beforehand paths or tracks for interconnecting the unit cells according to a given rule. Usually such determination or routing is made in the course of designing and manufacturing of the semiconductor integrated circuits.
The determination of vertical tracks in the interconnections of LSI is discussed in IEEE Trans. on CAD, vol. CAD-2, No. 4 (1983) pp 301-312. According to this article, it is attempted to shorten or minimize the lengths of the tracks by considering positional relationship between terminals or global or tentative routing.
When it is desired to determine a track pattern in LSI having a plurality of cell rows to interconnect the cell rows therein, through holes, terminals, or the like often become obstructions for tracks. In those cases, the tracks must be routed to bypass the obstructions. To attain this, the tracks can not be formed only by vertical track segments, but they must be formed by vertical track segments crossing (usually perpendicular to) each cell row and horizontal track segments parallel to each cell row in combination.
An interspace between any two adjacent cell rows decreases with the increase of a density with which the cell rows are provided. This limits the number of horizontal wiring channels or paths to be provided in each interspace.
The prior art as referred to above, However, gives no solution of the problem which would be caused by frequent use of interspaces to bypass the obstructions present in the global vertical paths. Since there is a limitation on the number of the horizontal tracks which can be provided in one interspace as described above, there may result incomplete LSIs in which some circuit elements left un-interconnected, especially in a master slice LSI, which has only limited wiring areas.
For example, if track routing is designed only with a view to shortening the lengths of the vertical paths, the horizontal paths will increase accordingly, and occasionally some terminals can not be interconnected, and remain un-interconnected.
FIG. 7 shows this situation. First, terminals 7 and 7 are interconnected by possible shortest path, which are composed of one vertical path segment 4 and two horizontal path segments 5, and then, terminals 8 and 8 are interconnected by one vertical path segment 4 and two horizontal path segments 5. Terminals 9 and 9 can not be interconnected after all because the vertical path segment 4 reserved, running between terminals 8 and 8 constitutes an obstruction and because no further space is left for horizontal path in the interspace between the first and second cell rows 1 and 1. As a consequence, terminals 9 and 9 remain un-interconnected as indicated by 2.
The path or track routing is carried out automatically with the aid of a computer. When such un-interconnected terminals result, they must be connected manually. Sometimes the redesigning of the track routing is necessitated. As a matter of course, these require extra cost and time.
This problem can be solved by enlarging the size of the semiconductor chip or by decreasing the number of the cells. The former recourse, however, will disadvantageously cause an increase of cost, and the latter recourse is not appropriate for LSIs.
Printed circuit boards each having a lot of circuit elements connected in a limited space, have the same problem. Also, the optical path layout in optical ICs has the same problem. It is not rare that some optical elements remain optically un-interconnected.
This problem, therefore, is general for a circuit structure having a plurality of terminal rows provided thereon, with each row having terminal pairs to be interconnected to each other. This problem requires an urgent solution.